Solid-state memory devices are generally configured as one or more arrays of rows and columns having storage locations at their points of intersection. Such devices may feature multiple sub-arrays (or “tiles”) within a single two-dimensional plane and/or multiple arrays stacked in three dimensions. Increasing the capacity of solid-state memory devices involves increasing the number and/or size of the arrays, and, as the storage capacity increases, achieving adequate yield becomes more difficult. In order to improve device yield, memory devices will often incorporate extra “spare” rows and/or columns. These spare rows and/or columns may then electrically replace rows or columns found to be defective during device testing. Other yield-improvement techniques include incorporating error-correcting mechanisms that enable a device to be used despite the presence of a defective row and/or column. However, due to, e.g., electrical interactions between rows and/or columns, often a defective row or column may cripple the performance of other columns or rows in the memory array (or even leave them inoperative). In such cases, the above-described yield enhancements may be insufficient to provide an operable device, and overall product yield decreases.